The present invention is directed to semiconductor devices and, more specifically, to thyristor-based memory devices and their fabrication on SOI wafers.
The semiconductor industry seems to continually strive for integrated circuits of greater density and complexity and, at the same time, seek reduced power consumption and package size. Recent advances, e.g., have brought forward single-die microprocessors with many millions of transistors that may operate at speeds of hundreds of millions of instructions per second. Such devices may now be packaged in relatively small semiconductor device packages either as stand-alones or together with other components as part of, e.g., a system on a chip (SOC).
An important part or component for most processing systems, including SOC solutions, is semiconductor memory. Conventional memory devices for storing digital data may include, e.g., SRAM and DRAM circuits. Typically, SRAMs have been used in applications calling for a high random access speed, while DRAMs, on the other hand, have been designated for high-density applications and those where a slower random access speed can be tolerated.
Recently, capacitively coupled thyristors have been introduced as a semiconductor memory that may provide both the speed of conventional SRAM and also the density of DRAM and as a solution that might also be accommodated with available CMOS processes. One type of thyristor-based memory may be described as a thin capacitively coupled thyristor (“TCCT”) and may be known to be operable as a bi-stable element.
One design consideration for such thyristor-based memory cell, including the TCCT memory cell, is the holding current of the thyristor. The holding current of the thyristor may refer to the minimum current required to preserve the thyristor's forward conducting state. One aim, therefore, is to target a holding current sufficiently low so that the memory cell may have an acceptable standby current. For example, a holding current larger than a few nano-Amperes per cell could significantly impact its power dissipation and limit the maximum capacity of a thyristor-based memory within, for example, an expanded memory array solution.
Another important consideration when using a thyristor-based memory cell may be its sensitivity to environmental factors that may cause error when it is in the blocking state. A thyristor may be vulnerable to error responsive to various adverse environmental conditions such as noise, light, anode-to-cathode voltage changes and high temperatures. Such vulnerability can affect the operation of the thyristor and result in undesirable disruption of the contents of the memory cell. Accordingly, there may be a compromise in the desire to reduce its vulnerability to adverse conditions and the desire to achieve low standby current.
Furthermore, during manufacture of a thyristor-based memory, various doping, implant, activation and anneal procedures may be performed. Some of these procedures may also be dependent on masking as may be used during patterning for the doping and implant provisions, as well as for patterning for other structures, such as polysilicon for the electrodes. These various procedures—e.g., patterning, masking, doping, implanting, siliciding annealing, etc.—for fabrication of the thyristor memory may, therefore, be understood to contribute to its overall manufacturing complexity, cost and size. The tolerances available for each of these procedures and associated limitations in their reproducibility may also be understood to impact product reliability and yields.